CERTIFICATION IN ADVANCED FPGA IMPLEMENTATION

COURSE OVERVIEW

  • This course gives deeper understanding of the Xilinx FPGA Design & Timing closure flow.
  • The course focuses on the subtleties of the Xilinx ISE flow and its add-on tools such as the PlanAhead, FPGA Editor and Constraints Editor. By mastering the tools and the design methodologies presented in this course, participants will be able to close the timing of their designs faster, and also shorten the development time, and lower development costs. This course combines insightful lectures with practical lab exercises to reinforce key concepts.

WHO WILL BENEFIT FROM THIS COURSE ?

  • VLSI Verification Engineers having knowledge in Verilog/VHDL, and willing to jump up their career with SystemVerilog / UVM skillset.
  • VLSI Engineers working in other areas (such as FPGA, STA, Design, etc), and willing to broaden their skills and explore opportunities to further grow up their career.
  • Freshers or Electronics students interested in pursuing VLSI Verification as career.

Trained Candidates So far

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COURSE SYLLABUS

Module1 : Timing Constraints

  • Clock constraints
  • Path Specific constraints
  • False path constraints
  • Input / Output path constraints
  • Specifying Clock regions
  • Viewing and Analyzing Timing Reports using Timing Analyzer

Module2 : Advanced Synthesis & Implementation flow

  • Synthesis Options
  • Translate Options
  • MAP Options
  • PAR Options
  • BitGen Options

Module3 : Advanced FPGA Timing closure flow

  • Typical FPGA Timing closure flow
    • RTL coding Techniques
    • XCF Constraints
    • Effective Floorplanning
    • Editing UCF Constraints

Module4 : Advanced FPGA Implementation for higher performance

  • Hierarchical Synthesis
  • Relationally Placed Macros
  • Optimizing critical path using FPGA Editor
  • Re-entrant Routing

Module5 : Mini Project

  • Standard mini projects will be exercised

HAVE ANY QUERIES ?

If you have any queries related to this training, please feel free to contact us. We will be more than happy to assist you at the earliest possible.

COMPANIES HIRING

TRAINING TESTIMONIALS & PLACEMENTS

PREREQUISITES

  • Basic knowledge on FPGA design flow
  • Basic knowledge on Verilog / VHDL

ADMISSION PROCEDURE

All the eligible interested candidates have to go through formal written test followed by personal interview. Written test format is composed of basic fpga design flow and verilog/vhdl.

Working professionals in any stream will get direct admission to this program, they need not appear for any written test / personal interview. However, they need to submit the State of Purpose to take up the course.

GRADING & CERTIFICATION

All the participants who fulfilled course assignments, case studies and assessments would be awarded with "Certification in Advanced FPGA Implementation"

PLACEMENT ASSISTANCE

All the eligible participants who have fulfilled requirements of the course will be given 100% placement assistance through our dedicated placement cell. As a part of the placement process, all the participants were assisted with preparing professional resume.

ALUMNI STATUS

All the eligible participants who have fulfilled the requirements of course will be given ALUMNI status. Apart from getting access to strong network of previous alumnus, they will be receiving latest technical articles, industry happenings and several job postings on first-hand.