• VLSI Design today has acquired the status of the most happening field in Electronics. It is a highly specialized field that has the power of integrating millions of transistors on a single Silicon Chip. VLSI is finding its extensive applications in Consumer Electronics, Defense, Aerospace, Set Top Entertainment Boxes, Computer Peripherals, Satellites, Cell Phones, and many more.
  • Further growing technological requirements have created an unprecedented demand for design of VLSI Design. That fuelled huge demand for the professionals in this area of expertise. SiON is now offering career courses geared towards meeting this rising global demand.


  • VLSI Verification Engineers having knowledge in Verilog/VHDL, and willing to jump up their career with SystemVerilog / UVM skillset.
  • VLSI Engineers working in other areas (such as FPGA, STA, Design, etc), and willing to broaden their skills and explore opportunities to further grow up their career.
  • Freshers or Electronics students interested in pursuing VLSI Verification as career.

Trained Candidates So far


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Module1 : Digital Logic Design

  • Introduction to Digital logic
  • Number Systems
  • Boolean algebra
  • Boolean minimization
  • Combinational circuit design
  • Sequential circuit design
  • Finite state machines
  • Designing complex digital circuits
  • Logic families
  • Miscellaneous concepts

Module2 : Project Management

  • GVim Editor
  • Linux Environment
  • Perl Scripting

Module3 : RTL Coding using Verilog HDL

  • Introduction to HDLs
  • Basic constructs
  • Syntax
  • Modeling styles
  • Combinational circuit design
  • Sequential circuit design
  • Finite state machine design
  • Digital system design
  • Simulation & Synthesis issues
  • Unwanted Latches
  • Clock-gating
  • Clock-domain crossing issues
  • Low power techniques
  • RTL Design strategies

Module4 : Functional Verification using Verilog HDL

  • Delay Concepts
  • Tasks & Functions
  • Stimulus generation
  • Race conditions
  • File IO Operations
  • Miscellaneous constructs
  • System Tasks
  • Compiler directives
  • Verification Process
  • Test bench structures
  • Bus function models
  • Assertion based Verification
  • Functional Verification Coverage
    • Statement
    • Branch
    • Expression
    • Path
    • Toggle

Module5 : Mini Project - using Verilog

  • Standard mini projects will be exercised

Module6 : Overview of Interface protocols:

  • UART
  • I2C
  • SPI
  • APB
  • AHB
  • AXI
  • Glimpse of USB
  • Glimpse of PCIe

Module7 : Overview of SoC Architectures:

  • What is an SoC ?
  • Advantages of SoCs over conventional ASICs?
  • Typical components of an SoCs
  • Sample SoC Architectures

Module8 : Advanced Functional Verification using SystemVerilog:

  • Importance of Functional verification in Chip design
  • Evolution of SystemVerilog
  • New Additions to SystemVerilog
    • New features
    • Data types
    • Arrays
    • Operators
    • Subroutines
    • Procedural statements
  • Concurrency
  • Interfaces
  • Object Oriented Programming
    • Encapsulation
    • Randomization
    • Inheritance & Polymorphism
  • Virtual Interfaces
  • Inter thread mechanism
  • Callbacks
  • Assertions
  • Functional Coverage
  • DPI
  • Layered testbench architecture
    • Driver
    • Monitor
    • Transactor
    • Generator
    • Scoreboard
    • Reference models
    • Bus function models
  • Testplan creation

Module9 : Advanced Functional Verification using UVM Methodology:

  • What are methodologies? Why?
  • Evolution of Verification methodologies
  • Introduction to UVM
  • Overview of UVM Environment
  • UVM Library
  • UVM Phasing
  • UVM Reporting
  • UVM Transactions
  • TLM Basics
  • UVM Configuration
  • UVM Driver
  • UVM Sequence, Sequencer and Virtual Sequencers
  • UVM Monitor
  • UVM Agent
  • UVM Factory
  • UVM Callbacks
  • UVM Coverage
  • UVM Register layer

Module10 : Advanced features of EDASimulator for effective debugging of SystemVerilog/UVM:

  • Waveform dumping
  • Forming on-the-fly expressions
  • Tracing drivers for "x" or wrong values
  • Debugging of dynamic objects
  • Debugging of constraints
  • Debugging of assertions

Module11 : Mini Project - using SystemVerilog:

  • Standard mini projects will be exercised

Module12 : Overview of ASIC EDA Flow:

  • Logic Synthesis Concepts
  • Logic Minimization
  • FSM Minimization
  • Optimization Techniques
  • Basic Timing Concepts
  • Fixing Setup, Holdtime violations
  • Formal Verification
  • Design-For-Testability
  • Scan Insertion
  • BIST
  • Placement
  • Routing
  • Floorplanning
  • Parasitic Extraction
  • Back-Annotation
  • GDS-II

Module13 : Advanced FPGA Implementation:

  • Evolution of Programmable logic
  • FPGAs Vs ASICs
  • Xilinx FPGA Architecture
    • Essential Building blocks
    • LUT
    • Slices
    • CLBs
    • Block Memories
    • DSP / Multipliers
    • Clock Management components
    • Processor
    • IO Pins
  • FPGA Design flow & Implementation
  • Reading reports
  • Pin Assignments
  • Timing & Area Constraints
  • DCMs
  • Memories & FIFOs
  • Timing closure strategy
  • Power estimation
  • Floorplanning the design
  • Back-annotation simulations
  • FPGA Board Overview
  • FPGA Configuration
  • System Testing
  • On-board stimulus generation
  • Logic state capturing
  • On-board debugging strategy
  • Overview of Embedded Systems design using FPGAs

Module14 : Industry standard Project:

  • Standard Industry project

Module15 : Virtual Interview Workshops:

  • Virtual interviews on various aspects of VLSI Design


If you have any queries related to this training, please feel free to contact us. We will be more than happy to assist you at the earliest possible.




  • B.E / B.Tech / M.E / M.Tech with background in Electronics, should have minimum aggregate of 60% throughout academic career
  • Basic knowledge in Verilog
  • Good knowledge on Digital design
  • Good knowledge on any Processor architectures
  • Good logical & analytical ability


All the eligible interested candidates have to go through formal written test followed by personal interview. Written test format is composed of Digital, Processor architecture, Analytical and Logical questions. Please walkin/mail/call us to schedule for written test & personal interview. Outstanding performers in the test may be awarded with partial / full scholarships.

Working professionals in any stream will get direct admission to this program, they need not appear for any written test / personal interview. However, they need to submit the State of Purpose to take up the course.


All the participants who fulfilled course assignments, case studies and final exams would be awarded with "Advanced Certification in VLSI Design & Verification"


All the eligible participants who have fulfilled requirements of the course will be given 100% placement assistance through our dedicated placement cell. As a part of the placement process, all the participants were assisted with preparing professional resume.


All the eligible participants who have fulfilled the requirements of course will be given ALUMNI status. Apart from getting access to strong network of previous alumnus, they will be receiving latest technical articles, industry happenings and several job postings on first-hand.