PCIe PROTOCOL for VLSI Professionals

COURSE OVERVIEW

  • Semiconductor industry is seeing huge jump in its market very recently, with more focus on high speed designs and architectures. This is where the industry is looking for professionals with key skills on any of the high speed interface protocols, such as PCIe, USB or AXI.
  • This course is intended to give a deeper overview of PCIe protocol including HandsOn sessions. Currently, this course is designed for VLSI Professionals (Design as well as Verification Engineers) having minimum 2 yrs of Industry experience.
  • The topics discussed in this course include a evolution of PCIe Gen 4.0, in detailed discussion of each of the protocol layers and their architecture - both in terms of Design as well as Verification, PCIe Configuration, Address mapping and Interrupts & Errors.
  • Participants will learn the internals of PCIe protocol and will get deeper understanding of all the PCIe protocol layers.
  • Instructor for this course is having over 14yrs+ experience in the VLSI industry with specialized expertize in PCIe protocol layers, bring up & performance measurement.

WHO WILL BENEFIT FROM THIS COURSE ?

  • VLSI Professionals (Design as well as Verification Engineers) who having knowledge in Verilog/VHDL, and willing to jump up their career with SystemVerilog / UVM skillset.
  • VLSI Engineers working in other areas (such as FPGA, STA, Design, etc), and willing to broaden their skills and explore opportunities to further grow up their career.

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COURSE SYLLABUS

Module1 : PCI Evolution

  • PCI Basic
  • PCI Bus Architecture
  • PCI Bus Arbitrator
  • PCI Inefficiency
  • PCI Interrupt Handling
  • PCI Error Handling
  • PCI Error Space map
  • PCI Configuration

Module2 : Overview of PCIe Architecture

  • Introduction of PCI Express
  • PCIe Layered Architecture
  • Types of Layers
  • Transaction Later
  • Data Link Layer
  • Physical layer
  • Ordered Set Packet Format Overview
  • Protocol Overview

Module3 : PCIe Configuration & Address mapping

  • PCI Express Configuration
  • PCI-Compatible Configuration Mechanism
  • Type 0 Configuration Request
  • Type 1 Configuration Request
  • Initial Configuration Accesses
  • PCI Express Enumeration
    • Single Root Complex
    • Multiple Root Complex
  • Memorize Identity
  • Root Complex Register Blocks (RCRBs)

Module4 : Transaction Layer

  • PCIe Transaction Layer
  • TLP Assembly and Disassembly
  • TLP Structure
  • Generic TLP Header format
  • Generic Header Field format
  • Transaction Descriptor format
    • Transaction ID
    • Traffic ID
    • Transaction Attributes
  • Request & Completion of TLP
    • IO Request
    • Memory Request
    • Configuration Request
    • Message Request
  • Address Routing
    • Address based Routing
    • ID based Routing
    • Implicit Routing
  • Example TLP packet flow

Module5 : Data Link Layer

  • Introduction
  • DLLP Packet types
  • DLLP Transmitter
  • DLLP Receiver
  • Flow Control Management
  • ACK/NAK Protocol
  • Power Management
  • Vender Specification DLLPs Format

Module6 : Physical Layer

  • PHY Layer Overview
  • Overview of PHY Transmit Logic
  • Overview of PHY Receiver Logic
  • Byte Stripping / Unstripping
  • Scrambling / Descrambling
  • 8/10b Encoding / Decoding
  • 128/130b Encoding / Decoding
  • PHY Layer Error Handling

Module7 : Virtual Channels

  • QoS/TCs/VCs and Arbitration
  • Quality of Service
  • Isochronous Transaction Support
  • Differentiated Services
  • Perspective on QOS/TC/VC and Arbitration
  • Traffic Classes and Virtual Channels
  • VC Assignment and TC Mapping
  • Arbitration
  • Virtual Channel Arbitration
  • Port Arbitration
  • Switch Arbitration

Module8 : Virtualization Overview

Module9 : Interrupts & Error Handling

Module10 : Hands-On sessions

Scheduled Date

18th Feb 2017

Duration

8 Days (4 Weekends)

Fees

Rs.59,000 /-

PCIe TRAINING TESTIMONIALS

APPLY HERE

If you would like to apply for this course (OR) If you have any queries related to this training, please feel free to contact us. We will revert to you at the earliest possible.

PREREQUISITES

  • Minimum 2 Yrs experience in VLSI Design / Verification
  • Working experience in Verilog/SV/VHDL
  • Good knowledge on any Processor architectures
  • Good logical & analytical ability

PLACEMENT ASSISTANCE

We can assist all the eligible participants with promising job opportunities within our client network. As a part of the placement process, all the participants will be assisted with preparing professional resume.