Advanced Verification using SYSTEMVERILOG & UVM


  • The introduction of the iPhone in 2007 represented a drift shift in electronic system design: moving advanced processing power off of the desktop and into the hands of users everywhere, always. This shift has led integrating ever-greater system complexity onto a singlechip. Today, a leading electronic system that is based on a SoC contains more than a billion gates and millions of lines of code. This increase in SoC design complexity has created manifold challenges in SoC verification. This not only is fuelled need for advancements in verification technologies, but also created huge need for the professionals in functional verification of SoC designs to achieve time to market.
  • This training is a thorough dive into advanced functional verification technologies such as SystemVerilog and UVM. It provides a step-by-step guide to build scalable, reusable and flexible verification environment to verify complex SoC designs.
  • This course combines insightful lectures with practical lab exercises to reinforce key concepts.


  • VLSI Verification Engineers having knowledge in Verilog/VHDL, and willing to jump up their career with SystemVerilog / UVM skillset.
  • VLSI Engineers working in other areas (such as FPGA, STA, Design, etc), and willing to broaden their skills and explore opportunities to further grow up their career.
  • Freshers or Electronics students interested in pursuing VLSI Verification as career.

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Module1 : Introduction to Functional Verification

  • What is Verification?
  • What do we verify?
  • Verification Abstractions
    • Behavioral level
    • Transaction level
    • Functional / RTL level
    • Gate level
    • Transaction level
  • Importance of (Functional) Verification in Chip design life cycle
  • Verification goals
  • Overview of various Functional Verification techniques
    • Simulations
    • FPGA Prototyping
    • Emulation
    • HW/SW Co-verification
    • Formal Verification
    • Semiformal Verification
  • Models of Functional Verification
    • Black box
    • White box
    • Gray box
  • Verification Hierarchy
    • Chip-level
    • Cluster / Subsystem level
    • IP level
    • Module / Unit level

Module2 : Overview of Interfce protocols

  • UART
  • I2C
  • SPI
  • APB
  • AHB
  • AXI
  • Glimpse of USB
  • Glimpse of PCIe

Module3 : Overview of SoC Architectures

  • What is an SoC ?
  • Advantages of SoCs over conventional ASICs?
  • Typical components of an SoCs
  • Sample SoC Architectures

Module4 : Overview of Functional Verification Environment Architectures

  • Typical SoC based Testbench environment
  • Stimuli Generators
    • Hard coded
    • Direct Stimuli from the environment
    • Stimuli from the model of the environment (BFMs)
    • Random Stimuli Generation
  • Predictors
    • Golden/Reference Model
    • More Abstract (Functional, Transaction Level)
    • Hardwired Response
    • Response database
  • Transactors
  • Monitors
  • Scoreboards
  • Coverage Collectors - Coverpoints
  • Property Checkers - Assertions

Module5 : Verification Management

  • Industry standard Functional Verification flow
  • Verification Specification Document
  • Testplan Document
  • Regression management
  • Test-run time management
  • EDA Licenses management
  • Computer resources management
  • Effective Debug management
    • Perl Scripting
    • Awk Scripting
    • Linux Shell scripting
    • Advanced Gvim usage
  • Bug management
  • Verification signoff criteria

Module6 : SystemVerilog Language Concepts:

  • Evolution of SystemVerilog : Why not Verilog / VHDL ?
  • Additions to SystemVerilog from Verilog 2001
    • New features
    • New Data type additions
    • Arrays - Fixed, Packed, Dynamic, Queues, Associated
    • Structures & Unions
    • New Operators
    • New additions to Subroutines
    • New additions to Procedural statements& Control flow
  • Concurrency
    • Fork.join
    • Fork..join_any
    • Fork..join_none
    • Automatic Variables
  • Interfaces
  • Program block
  • Object Oriented Programming
    • Classes : Encapsulating properties & methods
    • Object memory creation
    • Working with Object handles
    • Object copying : Shallow and Deep copy
    • Object cloning
    • Object protection
    • Object variables Vs Class variables : Static keyword
    • Object Randomization
    • Randomization Seed - A deep look
    • Randomization variables
    • Constraint Block
    • Weighted Randomization
    • Controlling Randomization
    • Solve order
    • Inline Constraints - with constraints
    • Object Inheritance
    • Limitations of Inheritance
    • Polymorphism and Methods overriding
  • Virtual Interfaces
  • Inter thread Synchronization & Communication
    • Events
    • Semaphores
    • Mailboxes
  • Packages
  • Assertions
    • Immediate assertions
    • Procedural assertions
    • Temporal operators
    • Boolean operators
    • Sequences
    • Properties
  • Functional Coverage
    • Coverpoints & Bins
    • Covergroups
    • Cross coverage
    • Sampling coverpoints
    • Calculating functional coverage
  • Interfacing with C - DPI
  • Compiler Directives

Module7 : Advanced Testbench Design using SystemVerilog:

  • Introduction to Layered testbench architecture
  • Driver
  • Monitor
  • Transactor
  • Generator
  • Configurations - Device, Transaction
  • Scoreboard
  • Reference models
  • Bus function models

Module8 : Advanced features of EDASimulator for effective debugging of SystemVerilog:

  • Waveform dumping
  • Forming on-the-fly expressions
  • Tracing drivers for "x" or wrong values
  • Debugging of dynamic objects
  • Debugging of constraints
  • Debugging of assertions

Module9 : Mini Project - using SystemVerilog:

  • Layered testbench for SRAM, Dual port SRAM, UART

Module10: UVM Methodology Concepts:

  • What are methodologies? Why?
  • Evolution of Verification methodologies
  • Introduction to UVM
  • Overview of UVM Environment
  • UVM Library
  • UVM Phasing
  • UVM Reporting
  • UVM Transactions
  • TLM Basics
  • UVM Configuration
  • UVM Driver
  • UVM Sequence, Sequencer and Virtual Sequencers
  • UVM Monitor
  • UVM Agent
  • UVM Factory
  • UVM Callbacks
  • UVM Register layer

Module11 : Developing Reusable Testbenches using UVM:

  • Modeling Data Items for Generation
  • Creating the Driver
  • Creating the Sequencer
  • Creating the Monitor
  • Instantiating Components
  • Creating the Agent
  • Creating the Environment
  • Transaction-Level Components
  • Enabling Scenario Creation
  • Managing End of Test
  • Implementing Checks and Coverage

Module12 : Mini Project - using UVM:

  • Layered testbench for SPI, APB

Module13 : Industry Standard Project:

  • Advanced reusable layered testbench for AXI, USB, PCIe, DDR4, etc.

Module14 : Virtual Interview Workshops:

  • Virtual interviews on Systemverilog, UVM


If you have any queries related to this training, please feel free to contact us. We will be more than happy to assist you at the earliest possible.




  • B.E / B.Tech / M.E / M.Tech with background in Electronics, should have minimum aggregate of 60% throughout academic career
  • Basic knowledge in Verilog
  • Good knowledge on Digital design
  • Good knowledge on any Processor architectures
  • Good logical & analytical ability


All the eligible interested candidates have to go through formal written test followed by personal interview. Written test format is composed of Digital, Processor architecture, Analytical and Logical questions. Please walkin/mail/call us to schedule for written test & personal interview. Outstanding performers in the test may be awarded with partial / full scholarships.

Working professionals in any stream will get direct admission to this program, they need not appear for any written test / personal interview. However, they need to submit the State of Purpose to take up the course.


All the participants who fulfilled course assignments, case studies and final exams would be awarded with "Advanced Certification in SoC Verification using Systemverilog / UVM"


All the eligible participants who have fulfilled requirements of the course will be given 100% placement assistance through our dedicated placement cell. As a part of the placement process, all the participants were assisted with preparing professional resume.

In addition, eligible fresher participants will be given Internship opportunity to work directly with our development team, until they get placed outside.


All the eligible participants who have fulfilled the requirements of course will be given ALUMNI status. Apart from getting access to strong network of previous alumnus, they will be receiving latest technical articles, industry happenings and several job postings on first-hand.